CMTUARTPAD=0, I2SSRC=00, FBSL=00, MCGCLKSEL=0, SDHCSRC=00, PLLFLLSEL=0, TIMESRC=00, USBSRC=0, TRACECLKSEL=0
System Options Register 2
| MCGCLKSEL | MCG clock select 0 (0): System oscillator (OSCCLK) 1 (1): 32 kHz RTC oscillator |
| FBSL | FlexBus security level 0 (00): All off-chip accesses (instruction and data) via the FlexBus are disallowed. 1 (01): All off-chip accesses (instruction and data) via the FlexBus are disallowed. 2 (10): Off-chip instruction accesses are disallowed. Data accesses are allowed. 3 (11): Off-chip instruction accesses and data accesses are allowed. |
| CMTUARTPAD | CMT/UART pad drive strength 0 (0): Single-pad drive strength for CMT IRO or UART0_TXD. 1 (1): Dual-pad drive strength for CMT IRO or UART0_TXD. |
| TRACECLKSEL | Debug trace clock select 0 (0): MCGOUTCLK 1 (1): Core/system clock |
| PLLFLLSEL | PLL/FLL clock select 0 (0): MCGFLLCLK clock 1 (1): MCGPLLCLK clock |
| USBSRC | USB clock source select 0 (0): External bypass clock (USB_CLKIN). 1 (1): MCGPLLCLK/MCGFLLCLK clock divided by the USB fractional divider. See the SIM_CLKDIV2[USBFRAC, USBDIV] descriptions. |
| TIMESRC | IEEE 1588 timestamp clock source select 0 (00): Core/system clock. 1 (01): MCGPLLCLK/MCGFLLCLK clock 2 (10): OSCERCLK clock 3 (11): External bypass clock (ENET_1588_CLKIN). |
| I2SSRC | I2S master clock source select 0 (00): Core/system clock divided by the I2S fractional clock divider. See the SIM_CLKDIV2[I2SFRAC, I2SDIV] descriptions. 1 (01): MCGPLLCLK/MCGFLLCLK clock divided by the I2S fractional clock divider. See the SIM_CLKDIV2[I2SFRAC, I2SDIV] descriptions. 2 (10): OSCERCLK clock 3 (11): External bypass clock (I2S0_CLKIN) |
| SDHCSRC | SDHC clock source select 0 (00): Core/system clock. 1 (01): MCGPLLCLK/MCGFLLCLK clock 2 (10): OSCERCLK clock 3 (11): External bypass clock (SDHC0_CLKIN) |